It is well known that for most cases of metal contacts to compound semiconductor materials the height of a Schottky barrier is independent of the electronic properties of the applied metal. This is in contrast to the ideal situation encountered for metal contacts to elemental semiconductors, such as silicon.
The familiar Schottky relationship is expressed in Equation 1 as follows. EQU .phi..sub.bn =.phi..sub.m -.chi..sub.sc Equation 1
where .phi..sub.bn is the barrier height on n type material
.phi..sub.m is the work function of the metal PA1 .chi..sub.sc is the electron affinity of the semiconductor which in turn is the energy required to remove an electron from the bottom of the conduction band to vacuum with no kinetic energy.
In the compound semiconductor/metal situation, the observed Schottky barrier height .phi..sub.b does not usually obey Equation 1.
It is recognized in the art that the insensitivity of the barrier at the metal/compound semiconductor interface to metal work functions is due to pinning at the interface of the Fermi level at a fixed energy within the band gap of the compound semiconductor material. This situation is termed "Fermi level pinning".
It is also clear that the Fermi level pinning condition is detrimental to Metal Oxide Semiconductor (MOS) structures. This is reported in J. Vac. Sci. Technol. 19 (3) Sept./Oct. 1981.
Because of the interfacial pinning, carrier flow across the interface and modulation of band bending in the semiconductor and resulting carrier density in MOS devices, cannot be easily controlled which, in turn, interferes with the performance of these devices.
Observations reported in Appl. Phys. Lett. 39, (9) 1 Nov. 81, p. 727, addressed the origin of Fermi level pinning and indicated that its presence correlated with anion clusters, for example, As in GaAs at the interface. That report further proposed an explanatory model which correlates the pinning energy with a Schottky barrier height that is consistent with the work function of the anion rich phases at the interface.
In studies reported in Japanese Journal of Applied Physics 19 (1980) Supplement 19-1, pp. 483-487, MOS structures made from gallium arsenide (GaAs) show that elemental As at the interface plays an important role in determining the electrical properties of the oxide. The electrical measurements show that excess elemental As is correlated with large trap densities and fixed states in the oxide.
Further, in studies reported in J. Vac. Sci. Technol., 14 4, July/Aug. 1977, p. 943, excess As originates from a pileup of elemental As at the oxide/GaAs interface during oxide growth and that this pileup is difficult to avoid and may contribute to the band bending with stabilization of the GaAs surface potential near mid-gap, in other words, Fermi level pinning. It is thus becoming clear in the art that identifying the origin of Fermi level pinning and controlling it is critical in achieving improved performance in both metal/compound semiconductor and metal/oxide/compound semiconductor devices.